High-performance digit-serial complex-number multiplier-accumulator
نویسندگان
چکیده
This paper presents a fast highly regular digit-serial complex-number multiplier-accumulator (CMAC) architecture which is well suited for V LSI implementations. This paper makes two contributions. First, several complex-number representation schemes are discussed. It is shown that the real-imaginary alternate (RIA) scheme is the best among all representation schemes and the prior designs of CMACs based on the radix-(2j) Redundant Complex Number System (RCNS) are not eecient with respect to hardware complexity and processing speed. Second, digit-serial CMAC architectures which can be pipelined at ne-grain level to increase the throughput rate are designed based on carry-save connguration.
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تاریخ انتشار 1998